1. Field of the Invention
The present invention relates to a silicon single crystal substrate and a method of manufacturing the same, and particularly to silicon single crystal substrates formed by slicing silicon single crystals grown by the Czochralski method and a method of manufacturing the silicon single crystals.
2. Background Art
Power devices mounted on cars, home appliances or the like should have a high breakdown voltage, and the resistance of the substrate affects the characteristics thereof. Therefore, a silicon wafer used as the substrate is required to be high in resistivity, with a low degree of variability.
Silicon single crystals used for substrates for power devices are generally manufactured by the Czochralski method (“CZ” method). With this CZ method, since the segregation coefficient of dopants such as boron and phosphorus with respect to the silicon single crystal is less than 1, dopant concentration in the silicon melt becomes higher as the silicon single crystal grows. Therefore, the dopant concentration in the grown silicon single crystal varies in the direction of the growth axis, and consequently, resistivity of the silicon single crystal also varies in the axial direction. Thus, it has been difficult to control resistivity.
Japanese Patent Laid-Open Application No. 2003-137687 describes a method of suppressing variation in resistivity in the direction of crystal growth by adding phosphorus corresponding to 25 to 30% of the boron concentration to an initial silicon melt, and growing the crystal by the Czochralski method.
Japanese Patent Laid-Open Application No. 2007-191350 describes a method of manufacturing a silicon single crystal wafer for an IGBT (Insulated Gate Bipolar Transistor) in which the variation in resistivity in a radial direction of the wafer is not higher than 5%.
Recently, a power semiconductor formed with a BCD (Bipolar Transistor, CMOS (Complementary Metal Oxide Semiconductor), and DMOS (Diffused Metal Oxide Semiconductor)) process has widely been used for applications where breakdown voltages are intermediate, i.e., up to 200 V. The BCD process refers to a process technique, in which a bipolar transistor used for analog process control, a fast operating CMOS suitable for a digital control circuit, and a DMOS suitable for controlling a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are integrated.
A silicon substrate for a power device manufactured by the BCD process is required to have uniform resistance in the substrate, few oxygen precipitates, or bulk micro defects (BMD), in the surface layer of the substrate, and a moderate amount of BMDs in a center of thickness of the substrate.
With the method described in Japanese Patent Laid-Open Application No. 2003-137687 the rate of change in resistivity in the axial growth direction up to a solidified fraction of 90% is high, and the quality required for BCD devices cannot be achieved. In addition, with the method described in Japanese Patent Laid-Open Application No. 2007-191350 the variation of resistivity in the radial direction is great, and the quality required of the BCD device thus also cannot be achieved. Moreover, a device described in Japanese Patent Laid-Open No. 2007-191350 is an IGBT, wherein current flows in a direction perpendicular to a surface of the substrate. Therefore, BMDs should be less across a direction of thickness of the substrate. Decrease in BMDs, however, leads to a lower capability for gettering heavy metals.